January 17, 2018

Arty Z7 Simple DVI Transmitter: Part 2 - Design Overview

Top level overview

SimpleDVITransmitter_block-1

Code

You can grab the full code from github. I'm using GNU Make to implement and simulate the design. I've only tested on Linux with GNU Make v4.1, didn't test on Windows so if the Windows version of Make gives you trouble just raise an issue on github. To build the bitstream you need to install Xilinx Vivado, I've tested with Vivado 2016.4 but newer versions should work as well. For simulation you can choose from Vivado xsim, Mentor Modelsim or GHDL+GTKWave. Tested with Vivado 2016.4, Modelsim 10.5b Intel FPGA starter edition, ghdl 0.36 (compiled from source) + GTKWave 3.3.79. Of course you can always use your own scripts or load the design in Vivado GUI

  • The src directory contains the VHDL code
  • sim contains a simple testbench and scripts used to run the simulation. The testbench is not self-checking and is meant to be used in GUI mode. It just loads the top level design in the simulator of choice so you can add signals in the waveform viewer of the simulator.
  • build contains the .xdc constraints file and scripts to run Vivado implementation.

Simulate the design and program the board

Open a terminal in the top directory and run make xsim. This will start a simulation in Vivado and run it for 1 us.
dvi_xsim
Before generating the bitstream first setup the board jumpers as in the following picture:
dvi_setup_arty
You will also need to:

  • Connect the board with a USB cable to your PC
  • Connect the HDMI OUT port of the board to the HDMI port of your monitor

Still in the top directory run make build. This will generate the bitstream in the build/bit directory.

Then, with the Arty connected to your PC run make program.
You should see 4 different colors alternating every ~2 seconds like in the (crappy) video below:

NOTE: The example code is hardcoded to 1920x1080@60Hz, however to achieve this resolution we need to exceed the FPGA's specifications (more details about this in the next post about clocking), so there are no guarantees that it's going to work on every Arty board. If you see that the demo fails in your setup, I have included in the code the settings needed to run at 1280x720 instead. You can find the relevant sections in dvi_tx_clkgen.vhd and rgb_timing.vhd. Just comment out the 1920x1080 settings and uncomment the 1280x720 ones.

Makefile options

make build

  • Builds the bitstream. The bitstream will be located in the build/bit folder. Generated reports are placed in build/reports

make program

  • Program the FPGA with the generated bitstream (you must first run make build to generate it). The Arty must be connected to the PC through the USB JTAG port.

make vsim

  • Simulates the design with Modelsim. Modelsim binaries must be in the PATH

make xsim

  • Simulates the design with Vivado xsim. Vivado binaries must be in the PATH

make ghld-gtkwave

  • Simulates the design with GHDL and loads it in the GTKWave viewer. Both GHDL and GTKWave binaries must be in the PATH

make clean

  • Cleans intermediate files generated by the tools. Doesn't clean the bit and reports folders

make lint

  • Disregard that option, it's just for personal use (linting code in Sublime text editor)
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