January 10, 2018

Arty Z7 Simple DVI Transmitter: Part 1 - Intro and DVI Primer

The Arty Z7 board

The Arty Z7 is a relatively new FPGA board from Digilent. It's an upgrade from their previous Arty board (now called Arty A7) with major improvements including a Zynq FPGA, gigabit Ethernet, 512MB (instead of 256MB) DDR and HDMI in/out ports. It comes in two flavors, the smaller Arty Z7-10 and the larger (in terms of LUTs/FFs/BRAMs) Arty Z7-20. My board is the Z7-20 and that's the one I'm going to use here.
Arty Z7
I'm not experienced with Zynq development, (never used it professionally or in hobby projects) and that's basically why I got the board. My plan is to start with a simple "Zynq-less" design and then gradually create a full IP core that I can connect to the Zynq, create drivers, etc. This series of blog posts will therefore serve as a personal "project diary" and hopefully as a tutorial for others.

I'm not going to go into details of how to set-up and use the board with Xilinx tools, you can find this info and more on Digilent's website. Digilent's documentation is very good and their forums are very active and helpful.

Why DVI?

  1. As I said above I will start with a "Zynq-less" design, the Zynq processor will not be involved, everything will be designed on the regular FPGA fabric. The problem with this approach is that a Zynq FPGA has two sets of pins, one set connected to the fabric (programmable logic or PL in Xilinx parlance) and one set connected to the Zynq processor (processing system or PS). The pins connected to the PS cannot be used directly by the PL (the other way around is allowed but not relevant at this point). Most of the peripherals on the Arty Z7 are connected to the PS and therefore need to instantiate the Zynq, but the HDMI pins (which will be used for DVI) are connected to the fabric.

  2. Video projects are cool :)

Why not HDMI?

DVI and HDMI interface signals are fully compatible and we can use an HDMI connector to transmit DVI. But why not just use HDMI? One can view HDMI as an extra step to DVI. While DVI is mostly used by PC monitors, HDMI has extra features (like audio, different color formats, remote control, even ethernet) which make it suitable for consumer electronics like TVs, but these extra features complicate the design. If we're only interested in RGB display and nothing more, DVI is great.

On top of that HDMI does not support all the display resolutions and refresh rates that DVI does (TVs where HDMI is mainly used are traditionally more limited than PC monitors). For example my PC monitor supports 1920x1080 @ 144 Hz through DVI, but it's limited to 1920x1080 @ 60 Hz through HDMI.

The Plan

First step: Simple DVI transmitter

  • No Zynq
  • Fixed display resolution (can't switch resolution on the fly, you need to rebuild the bitstream)
  • Max resolution 1080p (1920x1080 @ 60Hz)
  • Simple output pattern (no programmability)
  • No HDCP
  • No DDC

Second step: DVI transmitter + dynamic resolution switching

  • No Zynq
  • Max resolution 1080p (1920x1080 @ 60Hz)
  • Simple output pattern
  • No HDCP, no DDC

Third step: DVI transmitter, Zynq IP core

  • Simple stuff (little to no parametrization)
  • Minimal display driver
  • Max resolution 1080p (1920x1080 @ 60Hz)
  • A cool software demo
  • No HDCP, no DDC

Further steps (will see)

  • More configurable parameters
  • DDC (to read a monitor's EDID information)
  • No HDCP (I don't like DRM)

Prior work

  • Check out Mike Field's work not just for video projects but for FPGA projects in general. Really the best source of its kind up to this day (apparently he has a new site here but it's still not fully populated). His DVI encoder/decoder is used extensively in many open source projects.
  • Digilent offers an rgb2dvi core for free. It lacks timing signals though.
  • eewiki hosts an open source TMDS encoder.

Many more if you search around

DVI transmission

The DVI specification is described in Digital Visual Interface v1.0. In it's most basic form DVI is a digital version of VGA, it gets the same 8-bits per color RGB pixels and timing information, and transmits them serially using a 10-bit encoding format called TMDS. If you're not familiar with VGA there's a good tutorial and example design on eewiki. Go ahead and read it, especially the parts about signal timing, because the same concepts (blanking, vertical/horizontal sync, etc.) will appear a lot in these blog posts.
In the picture above Pixel Data carries the three 8-bit color values, CLK is the pixel clock, DE is the active data enable signal and Control Data carries a 2-bit control signal per color. Control data is transmitted during blanking time and pixel data during active time. The data enable signal indicates what type of data the transmitter should send, when it's high we're sending pixel data and when it's low control data. In DVI, from the total 6-bits of Control Data only 2 are used, to send the horizontal sync (hsync) and the vertical sync (vsync) signals.

In the TMDS transmitter each 8-bit color value has its separate TMDS encoder (and its own separate differential pair of wires) as can be seen in the following picture:
This is called single-link (or single-port) DVI. The pixel clock frequencies allowed in single-link mode are 25MHz to 165MHz. But modern monitors support resolutions and refresh rates that require pixel clock frequencies beyond 165MHz. Then there's "deep color", pixels with more than 8-bits per color. The solution to that is dual-link DVI, which as the name implies is comprised of two single-links (and twice the interface signals). In this series of posts I'm only going to focus on single-link basically because the Arty Z7 does not have a dual interface (and even if it had it can't handle the high frequency rates).

TMDS encoding

I talked about TMDS earlier which encodes 8-bit pixels to 10-bit signals. TMDS stands for Transmission Minimized Differential Signaling and it does three things:

  1. Uses differential signaling (2 wires per signal) to reduce noise
  2. Minimizes bit transitions to reduce EMI (electro-magnetic interference)
  3. Provides DC balancing (avoids long streams of 1's or 0's)

More details on an upcoming post about TMDS encoding.

Timing Standards

If you read the eewiki link above, there's an appendix at the end which lists VGA timings for many resolutions and refresh rates, however some of them are out of date (and it's missing the 16:9 "HD" ones). DVI capable monitors take their resolutions and timings from a standard published by VESA called Computer Display Monitor Timing (DMT). You can download the latest version (1.0 rev13) from the VESA website for free (needs registration). Here's a table with some common modes below:

Resolution Refresh Rate
Pixel Clock
Htotal Vertical
Vtotal Hpol Vpol
Hfront Hsync Hback Vfront Vsync Vback
640x480 60 25.175 16 96 48 800 10 2 33 525 - -
800x600 60 40.000 40 128 88 1056 1 4 23 628 + +
1024x768 60 65.000 24 136 160 1344 3 6 29 806 - -
1280x720 60 74.250 110 40 220 1650 5
5 20 750 + +
1280x800 60 83.500 72 128 200 1680 3 6 22 831 - +
1280x800 (RB) 60 71.000 48 32 80 1440 3 6 14 823 + -
1366x768 60 85.500 70 143 213 1792 3 3 24 798 + +
1440x900 60 106.500 80 152 232 1904 3 6 25 934 - +
1920x1080 60 148.500 88 44 148 2200 4 5 36 1125 + +
Htotal = Width + Hfront + Hsync + Hback
Vtotal = Height + Vfront + Vsync + Vback
Hpol: Horizontal sync polarity
Vpol: Vertical sync polarity

This only covers few common cases at 60Hz, for an exhaustive reference consult the DMT specification (not all monitors support all modes of course, you should also check your monitor's manual).

You may have noticed a duplicate entry for 1280x800, marked RB. This stands for Reduced Blanking. It's probably worth saying a couple of things about blanking. The defined blanking times in the standard were calculated with old CRT monitors in mind which needed considerable time to "reset" their electronics after each line and after each frame. Modern LCD (or other) monitors do not have such high restrictions and can do with lowered blanking times. Lowering the blanking time lowers the amount of data that has to be sent per frame and thus the pixel clock frequency to achieve a particular refresh rate.

So at some point VESA introduced Reduced Blanking modes for some resolutions, that target non-CRT monitors. This allows monitors to achieve resolutions and refresh rates that would be otherwise out of spec (either the model's specs or the DVI standard's specs). For example there's a 1920x1200@60Hz mode which has an equivalent RB duplicate. The standard mode requires a 193.250 MHz clock and the RB one 154.000 MHz. This means that the RB mode can be achieved with single-link DVI while the standard one requires dual-link.

On a side note, HDMI modes do not adhere to the VESA standard but to a standard published by CEA, called A DTV Profile for Uncompressed High Speed Digital Interfaces (or CEA-861 for short). That's not for free but I trust you are familiar with a website called Google :). Some pixel formats are common between HDMI and DVI (1920x1080@60Hz for example).

For the DVI project I'll be using DVI timings only (so no CEA stuff).

Comments powered by Disqus